1) Field of the Invention
The present invention relates to a one-chip first-in first-out (FIFO) memory device used in a digital television and a video tape recorder, and the like.
2) Description of the Related Art
In a digital television and a video tape recorder, and the like, a one-chip FIFO memory device is provided as a frame memory, to carry out an image processing and a stationary image processing, and the like.
In a prior art FIFO memory device, a write operation is carried out by using a sequentially-incremented write address, and a read operation is carried out by using a sequentially-incremented read address. Also, the write address is reset (cleared) by a write reset signal RSTW, and the read address is reset (cleared) by a read reset signal RSTR.
In the above-mentioned prior art FIFO memory device, however, if the write reset signal is the same as the read reset signal, the write operation is not synchronized with the read operation, since the speed of a read operation is substantially lower than that of a write operation. Accordingly, an external delay circuit must be connected to the FIFO memory device, to thus increase the cost of manufacturing the device, as will be later explained in detail.
In another prior art FIFO memory device, a special write buffer register and a special read buffer register are provided (Texas Instruments 1M bit Field Memory TMS4C1050). In this prior art, when a write reset signal RSTW is input to the device, a first series of data for a definite number of clock pulses (such as 4 clock pulses) are written into the special write buffer register. Thereafter, the other data are written via a write shift register into a memory cell array, and simultaneously, the data of the special write buffer register is transferred to the special read buffer register. On the other hand, when a read reset signal RSTR is input to the device, data is read out of the memory cell array to a read shift register. In this case, however, to compensate for a long read time, the data of the special read buffer register is first read out, and thereafter, the above-mentioned data of the memory cell array is read via the read shift register. Thus, this prior art requires complex special buffer registers, which increase the manufacturing cost.